W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 48

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of the eceived data is wrong. In
Bit 1: OER. This bit is set to a logical 1 to indicate that received data have been overwritten by the
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in
6.2.3
This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback,
Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally
Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS .
Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR .
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.
16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU
reads USR, it will clear this bit to a logical 0.
next received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
as follows:
(1) SOUT is forced to a logical 1, and SIN is isolated from the communication link instead of
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
bit is internally connected to the modem control input DCD .
connected to the modem control input RI .
Handshake Control Register (HCR) (Read/Write)
the TSR.
(bit 0 of HCR) → DSR , RTS ( bit 1 of HCR) → CTS , Loopback RI input ( bit 2 of HCR) →
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
RI and IRQ enable ( bit 3 of HCR) → DCD .
7
0
0
6
5
0
4
3
2
1
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0
W83877ATF/W83877ATG
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
Publication Release Date:November 2006
Version 1.0