W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 111

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Bit 1: Reserved.
IPD (Bit 0):
This bit is used to select W83877ATF/ATG's legacy power-down functions. When the bit 0 is set to 1,
W83877ATF/ATG will stop its clock internally and enter power-down (IPD) mode immediately.
W83877ATF/ATG will not leave the power-down mode until either a system power-on reset from the
MR pin occurs, or until this bit is reset to 0 to program the chip back to power-on state.
11.2.2 Configuration Register 1 (CR1), default = 00H
When the device is in Extended Function mode and EFIR is 01H, the CR1 register can be accessed
through EFDR. The bit definitions are as follows:
ABCHG (Bit 7):
This bit enables the FDC AB Change Mode. Default to be enabled at power-on reset.
Bit 6-bit 0: Reserved.
00
01
10
11
00
01
10
11
0
1
Drives A and B assigned as usual
Drive A and drive B assignments exchanged
Normal Mode (Default), PRTMOD2 = 0
Default state after power-on reset. In this mode, the W83877ATF is fully compatible with
the SPP and BPP mode.
Extension FDD Mode (EXTFDD), PRTMOD2 = 0
Reserved, PRTMOD2 = 0
Extension 2FDD Mode (EXT2FDD), PRTMOD2 = 0
Reserved, PRTMOD2 = 1
EPP Mode and SPP Mode, PRTMOD2 = 1
ECP Mode, PRTMOD2 = 1
ECP Mode and EPP Mode, PRTMOD2 = 1
7
6
5
4
3
- 104 -
2
W83877ATF/W83877ATG
1
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ABCHG