W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 133

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

11.2.25
When the device is in Extended Function mode and EFIR is 19H, the CR19 register can be accessed
through EFDR. The bit definitions are as follows:
This register is used for the high speed modem application. While the bit is set to logic 1, it can
increase the baudrate of UART to 921.2KBPS (the clock source of UART is 14.769MHz) for high
speed transmit/receive.
Bit 7 - bit 2: Reserved.
FASTA (Bit 1):
FASTB (Bit 0):
11.2.26
When the device is in Extended Function mode and EFIR is 20H, the CR20 register can be accessed
through EFDR. Default = FCH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
This register is used to select the base address of the Floppy Disk Controller (FDC) from 100H-3F0H
on 16-byte boundaries. NCS = 0 and A10 = 0 are required to access the FDC registers. A[3:0] are
always decoded as 0xxxb.
FDCAD7-FDCAD2 (Bit 7-bit 2): match A[9:4]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 1-bit 0: Reserved, fixed at zero.
0
1
0
1
Configuration Register 19 (CR19), default=00H
Configuration Register 20 (CR20)
7
the clock source of UART A is the same as the frequency of TURA (CR0C bit 7)
and SUAMIDI (CR3 bit 1) selected.
the clock source of UART A is 14.769MHZ.
the clock source of UART B is the same as the frequency of TURB (CR0C bit 6)
and SUBMIDI (CR3 bit 0) selected.
the clock source of UART B is 14.769MHZ.
6
7
5
6
4
5
3
4
2
3
- 126 -
1
2
0
W83877ATF/W83877ATG
1
FASTB
FASTA
reserved
reserved
reserved
reserved
reserved
reserved
0
reserved
reserved
FDCAD2
FDCAD3
FDCAD4
FDCAD5
FDCAD6
FDCAD7