W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 65

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.3.4
These registers are only used in advanced modes.
6.3.4.1. Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL)
The two registers are the same as the legacy UART baud rate divisor latch in SET 1. Reg0~1. When
using advanced UART/SIR/ASK-IR mode operation, these registers should be programmed to set
baud rate. This is to prevent a backward operation occurring.
6.3.4.2. Reg2 - Advanced UART Control Register 1 (ADCR1)
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Advanced
Reset Value
ADDRESS
OFFSET
MODE
UART
0
1
2
3
4
5
6
7
Set2 - Interrupt Status or UART FIFO Control Register (ISR/UFR)
BR_OUT
BR_OUT - Baud Rate Clock Output
Write to 1 enables the programmed baud rate clock to output to DTR pin. This bit is the
only test baud rate divisor.
Reserved, write 0.
EN_LOUT - Enable Loopback Output
Write to 1 enables output of transmitter data to IRTX pin during doing loopback operation.
Setting this bit can check output data with internal data.
D_CHSW - DMA TX/RX Channel Swap
If using signal DMA channel in MIR/FIR mode, then the DMA channel can be swapped.
Write to 1 enables output data during the ALOOP=1.
BIT 7
REGISTER
Reserved
0
RXFDTH
TXFDTH
ADCR1
ADCR2
NAME
ABHL
ABLL
SSR
BIT 6
0
-
D_CHSW
Advanced Baud Rate Divisor Latch (Low Byte)
Advanced Baud Rate Divisor Latch (High Byte)
Advanced UART Control Register 1
Sets Select Register
Advanced UART Control Register 2
Transmitter FIFO Depth
Receiver FIFO Depth
0
1
EN_LOUT D_CHSW
BIT 5
0
BIT 4
- 58 -
0
DMA Channel Selected
REGISTER DESCRIPTION
Receiver (Default)
W83877ATF/W83877ATG
Transmitter
ALOOP
BIT 3
0
-
DMATHL
BIT 2
0
DMA_F
BIT 1
0
ADV_SL
BIT 0
0