W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 22

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5. FDC FUNCTIONAL DESCRIPTION
5.1
The floppy disk controller of the W83877ATF/ATG integrates all of the logic required for floppy disk
control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to
compatible values. The FIFO provides better system performance in multi-master systems. The digital
data separator supports up to data rate 1 M bits/sec or 2 M bits/sec.
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
5.1.1
The interface consists of the standard asynchronous signals: RD , WR , A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
5.1.2
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and
DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage
of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with a FIFO. The data are based upon the following
formula:
W83877ATF/ATG FDC
FIFO THRESHOLD
AT interface
FIFO (Data)
FIFO THRESHOLD
15 Byte
15 Byte
2 Byte
8 Byte
1 Byte
2 Byte
8 Byte
1 Byte
THRESHOLD × (1/Data Rate) *8 - 1.5 μ S = DELAY
2 × 16 μ S - 1.5 μ S = 30.5 μ S
8 × 16 μ S - 1.5 μ S = 6.5 μ S
15 × 16 μ S - 1.5 μ S = 238.5 μ S
1 × 8 μ S - 1.5 μ S = 6.5 μ S
2 × 8 μ S - 1.5 μ S = 14.5 μ S
8 × 8 μ S - 1.5 μ S = 62.5 μ S
15 × 8 μ S - 1.5 μ S = 118.5 μ S
1 × 16 μ S - 1.5 μ S = 14.5 μ S
MAXIMUM DELAY TO SERVICING AT 500K BPS
MAXIMUM DELAY TO SERVICING AT 1M BPS
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W83877ATF/W83877ATG
Data Rate
Data Rate
Publication Release Date:November 2006
Version 1.0