W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 159

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

W83877ATF/W83877ATG
For the BIOS software to raise an event to the ACPI software, BIOS_RLS, GBL_EN, and GBL_STS
bits are involved. GBL_EN is the enable bit and the GBL_STS is the status bit. Both are controlled by
the ACPI software. If BIOS_RLS is set by the BIOS software and GBL_EN is set by the ACPI
software, an SCI interrupt is raised. Writing a 1 to BIOS_RLS sets it to logic 1 and also sets GBL_STS
to logic 1; Writing a 0 to BIOS_RLS has no effect. Writing a 1 to GBL_STS clears it to logic 0 and also
clears BIOS_RLS to logic 0; writing a 0 to GBL_STS has no effect.
For the ACPI software to raise an event to the BIOS software, GBL_RLS, BIOS_EN, and BIOS_STS
bits are involved. BIOS_EN is the enable bit and the BIOS_STS is the status bit. Both are controlled
by the BIOS software. If GBL_RLS is set by the ACPI software and BIOS_EN is set by the BIOS
software, an SMI is raised. Writing a 1 to GBL_RLS sets it to logic 1 and also sets BIOS_STS to logic
1; Writing a 0 to GBL_RLS has no effect. Writing a 1 to BIOS_STS clears it to logic 0 and also clears
GBL_RLS to logic 0; writing a 0 to BIOS_STS has no effect.
For the bus master to raise an event to the ACPI software, BM_CNTRL, BM_RLD, and BM_STS bits
are involved. Both BM_RLD and BM_STS are controlled by the ACPI software. If BM_CNTRL is set
by the BIOS software and BM_RLD is set by the ACPI software, an SCI interrupt is raised. Writing a 1
to BM_CNTRL sets it to logic 1 and also sets BM_STS to logic 1; Writing a 0 to BM_CNTRL has no
effect. Writing a 1 to BM_STS clears it to logic 0 and also clears BM_CNTRL to logic 0; writing a 0 to
BM_STS has no effect.
11.3.2 Power Management Timer
In the ACPI specification, a power management timer is required. The power management timer is a
24-bit fixed rate free running count-up timer that runs off a 3.579545MHZ clock. The power
management timer has the corresponding status bit (TMR_STS) and enable bit (TMR_EN). The
TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the
TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Three registers are
used to read the timer value; they are located in the PM1 register block. The power management timer
has one enable bit (TMR_ON) to turn if on or off. The TMR_ON is located in GPE register block. If it is
cleared to 0, the power management timer function will not work. There are no timer reset
requirements, except that the timer should function after power-up. See the following figure for an
illustration.
TMR_STS
TMR_ON
24 bit
counter
To SCI Logic
Bits (23-0)
3.579545 MHz
24
TMR_EN
TMR_VAL
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