W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 84

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Bit 7:
Bit 6~4:
Bit 3:
Bit 2~0:
6.3.9.6. Set7.Reg5 - Infrared module (Front End) Select 2 (IRM_SL2)
Bit 7:
Bit 6~4:
Bit 3:
Bit 2~0:
6.3.9.7. Set7.Reg6 - Infrared module (Front End) Select 3 (IRM_SL3)
default Value
default Value
IRM_SL2
IRM_SL3
REG.
REG.
IR_MSP - IR mode Select Pulse
Write to 1 causes the transmitter (IRTX) to send a 64
end operational mode. When IR front-end module uses mode select pin (MD) and
transmitter IR pulse (IRTX) to switch high speed IR (such as FIR or MIR) or low speed IR
(SIR or ASK-IR), this bit should be used.
SIR_SL2~0 - SIR (Serial IR) mode select.
These bits are to program the operational mode of the SIR front-end module. These
values of SIR_SL2~0 will automatically load to pins of IR_SL2~0, respectively, when (1)
AM_FMT=1 (Automatic Format, in Set7.Reg7.Bit7), (2) the mode of Advanced UART is
set to SIR (AD_MD2~0, in Set0.Reg4.Bit7~0).
Reserved, write 0.
AIR_SL2~0 - ASK-IR mode Select.
These bits will setup the operational mode of ASK-IR front-end module when AM_FMT=1
and AD_MD2~0 are set to ASK-IR mode. These values will automatically load to
IR_SL2~0, respectively.
Reserved, write 0.
FIR_SL2~0 - FIR mode select.
These bits setup the operational mode of FIR front-end module when AM_FMT=1 and
AD_MD2~0 set to FIR mode. These values will automatically load to IR_SL2~0,
respectively.
Reserved, write 0.
MIR_SL2~0 - MIR mode Select.
These bits setup the MIR operational mode when AM_FMT=1 and AD_MD2~0 set to MIR
mode. These values will be automatically loaded to IR_SL2~0, respectively.
BIT 7
BIT 7
0
0
-
-
LRC_SL2 LRC_SL1 LRC_SL0
FIR_SL2
BIT 6
BIT 6
0
0
FIR_SL1
BIT 5
BIT 5
0
0
FIR_SL0
BIT 4
BIT 4
0
0
- 77 -
W83877ATF/W83877ATG
BIT 3
BIT 3
0
0
-
-
Publication Release Date:November 2006
μ
s pulse to setup a special IR front-
HRC_SL2 HRC_SL1 HRC_SL0
MIR_SL2 MIR_SL1 MIR_SL0
BIT 2
BIT 2
0
0
BIT 1
BIT 1
0
0
Version 1.0
BIT 0
BIT 0
0
0