W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 71

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

These are 13-bit registers. A write to these registers will cause the transmitter frame length of a
package be programmed. These registers are only used in APM=1 (automatic package mode,
Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame length
if the transmitted data is larger than the programmed frame length. When these registers are read,
they will return the number of bytes which have not been transmitted from a frame length
programmed.
6.3.6.5. Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH)
These are 13-bit registers which combine to form a 13-bit up counter. By programming these
registers, the receiver frame length will be limited to the programmed frame length. If the received
frame length is larger than the programmed receiver frame length, the bit of MX_LEX (Maximum
Length Exceed) will be set to 1. Simultaneously, the receiver will not receive any data to RX FIFO
until the next start flag in the next frame, which is defined in the physical layer IrDA 1.1, is reached;
the received data then begins to write to RX FIFO. Reading these registers will return the number of
received data bytes from the receiver for a frame.
6.3.7
6.3.7.1. Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
If flow control occurs from MIR/FIR mode change to SIR mode, then the pre-programming baud rate
of FCBLL/FCBHL is loaded to advanced baud rate divisor latch (ADBLL/ADBHL).
Reset Value
Reset Value
ADDRESS
RFRLH
OFFSET
RFRLL
REG.
0
1
2
3
4
5
6
7
Set 5 - Flow control and IR control and Frame Status FIFO registers
BIT 7
bit 7
REGISTER
0
-
-
RFRLFH
RFRLFL
IRCFG1
FCBHL
FC_MD
FCBLL
FS_FO
NAME
SSR
BIT 6
bit 6
0
-
-
Flow Control Baud Rate Divisor Latch Register (Low Byte)
Flow Control Baud Rate Divisor Latch Register (High Byte)
Flow Control Mode Operation
Sets Select Register
Infrared Config Register
Frame Status FIFO Register
Receiver Frame Length FIFO Low Byte
Receiver Frame Length FIFO High Byte
BIT 5
bit 5
0
-
-
bit 12
BIT 4
- 64 -
bit 4
0
0
REGISTER DESCRIPTION
W83877ATF/W83877ATG
bit 11
BIT 3
bit 3
0
0
bit 10
BIT 2
bit 2
0
0
BIT 1
bit 1
bit 9
0
0
BIT 0
bit 0
bit 8
0
0