PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 102

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

5.2.2
5.2.2.1 CFI Interface Signals
The configurable interface signals are summarized in the table below:
Table 14
Pin No.
40
41
42
43
38
37
36
35
34
33
1) Only EPIC-1
5.2.2.2 CFI Registers
The characteristics at the configurable interface (timing, modes of operation, etc. … ) are
programmed in the 6 CFI interface registers and the Operation Mode Register OMDR.
The function of each bit is described in chapter 5.2.2.3. For addresses refer to
chapter 4.1.
CFI Mode Register 1
CMD1
Semiconductor Group
1)
1)
1)
1)
Configurable Interface Configuration
bit 7
Symbol
DD0/SIP0
DD1/SIP1
DD2/SIP2
DD3/SIP3
DU0/SIP4
DU1/SIP5
DU2/SIP6
DU3/SIP7
FSC
DCL
CCS
CSM
I: Input
O: Output
O/IO
O/IO
O/IO
O/IO
I/IO
I/IO
I/IO
I/IO
I or O
I or O
CSP1
Function
Data downstream outputs in CFI modes 0, 1 and 2
(PCM and IOM applications).
Bidirectional serial interface ports in CFI mode 3
(SLD application).
Tristate or open drain output drivers selectable
(OMDR:COS).
Data upstream inputs in CFI modes 0, 1 and 2
(PCM and IOM applications).
Bidirectional serial interface ports in CFI mode 3
(SLD application).
Tristate or open drain output drivers for SIP lines
selectable (OMDR:COS).
Frame synchronization input (CMD1:CSS = 1) or
output (CMD1:CSS = 0).
Data clock input (CMD1:CSS = 1) or output
(CMD1:CSS = 0).
CSP0
102
read/write
CMD1
CMD0
reset value:
Application Hints
CIS1
PEB 2055
PEF 2055
bit 0
00
CIS0
H