PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 92

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Table 9
PCM Mode
0
1
2
Table 10
PCM Mode
0
1
2
In PCM mode 1 a PCM frame consisting of 24 time slots would require a setting of
PBNR = (24
In PCM mode 2 a PCM frame consisting of 64 time slots would require a setting of
PBNR = (64
PCM Bit Number PBNR:BNF7 … BNF0
The PCM data rate is determined by the clock frequency applied to the PDC pin and the
clock rate selected by PMOD:PCR. The number of bits which constitute a PCM frame
can be derived from this data rate by dividing by 8000 (8 kHz frame structure).
If the PCM interface is for example operated at 2.048 Mbit/s, the frame would consist of
256 bits or 32 time slots.
Note: There is a mode dependent restriction on the possible number of bits per frame
This number of bits must be programmed to PBNR:BNF7 … 0 as indicated in table 10.
The externally applied frame synchronization pulse PFS resets the internal PCM time
slot and bit counters. The value programmed to PBNR is internally used to reset the
PCM time slot and bit counters so that these counters always count modulo the actual
number of bits per frame even in the absence of the external PFS pulse. Additionally, the
PFS period is internally checked against the PBNR value. The result of this comparison
is displayed in the PCM Synchronization Status bit (STAR:PSS). Also, refer to
chapter 5.8.3.
Examples
In PCM mode 0 a PCM frame consisting of 32 time slots would require a setting of
PBNR = 32 8 – 1 = 255
Semiconductor Group
BPF:
8 – 2)/2 = 95
8 – 4)/4 = 127
D
D
= FF
D
= 5F
= 7F
Possible Values for BNF
BPF must be modulo 32
BPF must be modulo 64
BPF must be modulo 128
PBNR:BNF7 … 0(Hex)
BPF7 … 0 = BPF – 1
BPF7 … 0 = (BPF – 2)/2
BPF7 … 0 = (BPF – 4)/4
H
.
H
.
H
.
92
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