PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 219

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

ISTA:
SOV:
Interrupt Status Register
The ISTA register should be read after an interrupt in order to determine the interrupt
source. Two maskable (MASK) interrupts are provided in connection with the
synchronous transfer utility:
SIN:
Semiconductor Group
bit 7
TIN
Synchronous Transfer Interrupt; The SIN interrupt is enabled if at
least one synchronous transfer channel (A and/or B) is enabled via
the STCR:TAE, TBE bits. The SIN interrupt is generated when the
access window for the P opens. After the occurrence of the SIN
interrupt (logical 1) the P can read and/or write the synchronous
transfer data registers (STDA, STDB). The window where the P can
access the data registers is open for the duration of one frame
(125 s) minus 17 RCL cycles if only one synchronous channel is
enabled and it is open for one frame minus 33 RCL cycles if both A
and B channels are enabled. The SIN bit is reset by reading ISTA.
Synchronous Transfer Overflow; The SOV interrupt is generated
(logical 1) if the P fails to access the data registers (STDA, STDB)
within the access window. The SOV bit is reset by reading ISTA.
SFI
MFFI
MAC
219
read/write reset value:
PFI
PIM
Application Hints
SIN
00
PEB 2055
H
PEF 2055
bit 0
SOV