PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 199

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Status Register
STAR
The status register STAR displays the current state of the MFFIFO and of the monitor
transfer operation. It should be interrogated after an ISTA:MFFI interrupt and prior to
accessing the MFFIFO.
The STAR register bits do not generate interrupts and are not modified by reading
STAR.
MFTO:
MFAB:
MFAE:
MFRW:
MFFE:
Interrupt Status Register
ISTA
The ISTA register should be read after an interrupt in order to determine the interrupt
source. In connection with the monitor handler two maskable (MASK) interrupt bits are
provided by the EPIC:
MFFI:
MAC:
Semiconductor Group
bit 7
bit 7
MAC
TIN
MF Channel Transfer in Operation; an MF channel transfer is in
operation (1) or not (0).
MF Channel Transfer Aborted; a logical 1 indicates that the remote
receiver aborted a handshaked message transfer.
MFFIFO Access Enable; the MFFIFO may be either read or written to
(1) or it may not be accessed (0).
MFFIFO Read/Write; if MFAE is set to logical 1 the MFFIFO may be
read (1) or is ready to be written to (0).
MFFIFO Empty; the MFFIFO is empty (1) or not empty (1).
MFFIFO interrupt; if this bit is set to 1, the last MF channel command
(issued by CMDR:MFT1, MFT0) has been executed and the EPIC is
ready to accept the next command. Additional information can be
read from STAR:MFTO … MFFE. MFFI is reset by reading ISTA.
Monitor Channel Active Interrupt; this bit set to 1 indicates that the
EPIC has found an active monitor channel. A new search can be
started by reissuing the CMDR:MFSO command. MAC is reset by
reading ISTA.
TAC
SFI
MFFI
PSS
MFTO
read
read
MAC
199
MFAB
PFI
reset value:
reset value:
MFAE
PIM
Application Hints
MFRW
SIN
00
00
PEB 2055
H
H
PEF 2055
bit 0
bit 0
MFFE
SOV