PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 29

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

2.4
The memory block of the EPIC performs the switching functionality.
It consists of four sub blocks:
– Upstream data memory
– Downstream data memory
– Upstream control memory
– Downstream control memory.
The PCM-interface reads periodically from the upstream (writes periodically to the
downstream) data memory (cyclical access), see figure 17.
2.3
In order to optimize the on-board interchip communication, a very flexible serial interface
is available. It formats the data transmitted or received at the DDn-, DUn- or SIPn-lines.
Although it is typically used in IOM-2 or SLD-configuration to connect layer-1 devices,
application specific frame structures can be defined (e.g. to interface ADPCM-
converters or maintenance blocks).
Figure 16 shows the IOM-2 Interface structure in Line Card Mode:
Figure 16
IOM
Semiconductor Group
®
FSC
DCL
DU
DD
-2 Frame Structure with 2.048 Mbit/s Data Rate
Configurable Interface
Memory Structure and Switching
IOM
IOM
R
R
CH0
CH0
B1
B1
CH1
CH1
CH2
CH2
B2
B2
CH3
CH3
125 s
MONITOR
MONITOR
29
CH4
CH4
D(2)
CH5
CH5
C/I(6)
C/I(4)
CH6
CH6
M M
R X
M
R
Functional Description
M
X
for ISDN Lines
for Analog Lines
CH7
CH7
ITD00522
PEB 2055
CH8
CH8
PEF 2055