PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 222

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

The following register bits are used in conjunction with the hardware timer:
Timer Register
TIMR:
Writing to the TIMR register stops the timer operation!
SSR:
TVAL6 … 0:
Command Register
CMDR
ST:
TIG:
Semiconductor Group
bit 7
bit 7
SSR
0
Signaling Channel Sample Rate; this bit actually does not affect the
timer operation. It is used to select between a fixed last look period
for signaling channels of 125 s (SSR = 1), which is independent of
the timer operation and a signaling sample rate that is defined by the
timer period (SSR = 0).
Timer Value; The timer period is programmed here in increments of
250 s:
Timer period = (TVAL6 … 0 + 1)
Start Timer; setting this bit to logical 1 starts the timer to run cyclically
from 0 to the value programmed in TIMR:TVAL6 … 0. Setting this bit
to logical 0 does not affect the timer operation. If the timer shall be
stopped, the TIMR register must simply be written with a random
value.
Timer Interrupt Generation; setting this bit together with CMDR:ST to
logical 1 causes the EPIC to generate a periodic interrupt (ISTA:TIN)
each time the timer expires. Setting the TIG bit to logical 0 together
with the CMDR:ST bit set to logical 1 disables the interrupt
generation. It should be noted that this bit only controls the ISTA:TIN
interrupt generation and need not be set for the ISTA:SFI interrupt
generation.
TVAL6
ST
TVAL5
TIG
TVAL4
CFR
222
write
write
TVAL3
MFT1
250 s
reset value:
reset value:
TVAL2
MFT0
Application Hints
TVAL1
MFSO
00
00
PEB 2055
H
H
PEF 2055
bit 0
bit 0
TVAL0
MFR