PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 74

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Semiconductor Group
4.2.6.2 Timer Register (TIMR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
The EPIC timer can be used for 3 different purposes: timer interrupt generation
(ISTA:TIG), FSC multiframe generation (CMD2:FC2..0 = 111) and last look period
generation.
SSR
TVAL6..0 Timer Value bits 6..0; the timer period, equal to (1+TVAL6..0)
The timer is started as soon as CMDR:ST is set to 1 and stopped by writing the TIMR
register or by selecting OMDR:OMS0 = 0.
bit 7
SSR
Signaling Sampling Rate.
0… the last look period is defined by TVAL6..0.
1… the last look period is fixed to 125 s.
programmed here. It can thus be adjusted within the range of 250 s up to
32 ms.
TVAL6
H
TVAL5
TVAL4
74
TVAL3
write
write
Detailed Register Description
TVAL2
address: C
OMDR:RBS = 0
address: 18
TVAL2
PEB 2055
PEF 2055
H
bit 0
250 s, is
H
TVAL0