PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 65

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Access in multiplexed P-interface mode:
and downstream memory blocks. Bits MA6..0 encode the CFI or PCM port and time slot
number as in the following tables:
Table 3
Time Slot Encoding for Data Memory Accesses
PCM-mode 1,3
PCM-mode 2
4.2.3.2 Memory Access Address Register (MAAR)
Access in demultiplexed P-interface mode:
Reset value: xx
The Memory Access Address Register MAAR specifies the address of the memory
access. This address encodes a CFI time slot for control memory (CM) and a PCM time
slot for data memory (DM) accesses. Bit 7 of MAAR (U/D bit) selects between upstream
PCM-mode 0
Semiconductor Group
bit 7
U/D
MA6
H
MA5
bit U/D
bits MA6..MA3, MA0
bits MA2..MA1
bit U/D
bits MA6..MA3, MA1, MA0
bit MA2
bit U/D
bits MA6..MA0
Data Memory Address
MA4
65
MA3
read/write
read/write
Detailed Register Description
MA2
Direction selection
Time slot selection
Logical PCM port number
Direction selection
Time slot selection
Logical PCM port number
Direction selection
Time slot selection
address: 1
OMDR:RBS = 0
address: 02
MA1
PEB 2055
PEF 2055
H
bit 0
H
MA0