PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 64

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Semiconductor Group
b) Pre-processed Applications
Downstream:
Application
Decentral D channel handling
Central D channel handling
6-bit Signaling (e.g. analog IOM)
8-bit Signaling (e.g. SLD)
Upstream:
Application
Decentral D channel handling
Central D channel handling
6-bit Signaling (e.g. analog IOM)
8-bit Signaling (e.g. SLD)
c) P-access Applications
MACR:
5. Control-reading the upstream or downstream CM code.
MACR:
0
1
Setting CMC = 1001, initializes the corresponding CFI time slot to be
accessed by the P. Concurrently, the datum in MADR is written (as 8-bit
CFI-idle code) to the CM data field. The content of the CM data field is directly
exchanged with the corresponding time slot.
Note that once the CM code field has been initialized, the CM data field can
be written and read as described in subsection 3.
The CM code can then be read out of the 4 LSBs of the MADR register.
1
1
1
1
1
1
CMC = 1010
CMC = 1010
CMC = 1010
CMC = 1011
Even CM Address
CMC = 1000
CMC = 1010
Even CM Address
CMC = 1000
CMC = 1000
64
1
0
Detailed Register Description
0
0
CMC = 1011
CMC = 1011
CMC = 1010
CMC = 1011
Odd CM Address
CMC = 1011
CMC = PCM code for a
2-bit subtime slot
Odd CM Address
CMC = 0000
CMC = PCM code for a
2-bit subtime slot
0
0
PEB 2055
PEF 2055
1
0