PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 149

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Reading the up- or
downstream DM data field
Table 26
Summary of Memory Operations
Application
Writing a PCM idle value to
the upstream DM data field
The MACR value specifies
the bandwidth and bit
position at the PCM
interface
Writing to a single tristate
field location
Writing to all tristate field
locations
Reading a single tristate
field location
Writing to the CM data field 8 bit value
Semiconductor Group
MADR
8 bit, 4 bit or 2 bit idle
value to be transmitted
at the PCM interface
8 bit value transmitted
at the upstream or 8 bit
value received at the
downstream PCM
interface
Tristate information
contained in the
4 LSBs:
0 = tristated,
1 = active
Tristate information
contained in the
4 LSBs:
0 = tristated,
1 = active
Tristate information
contained in the 4
LSBs
(C/I value, pointer to
PCM interface, etc.)
149
MAAR
Address of the
(upstream) PCM
port and time
slot
Address of the
PCM port and
time slot
Address of the
(upstream) PCM
port and time
slot
Don’t care
Address of the
(upstream) PCM
port and time
slot
Address of the
CFI port and
time slot
Application Hints
MACR (Hex)
08
18
10
38
30
28
20
88
60
68
E0
48
H
H
H
H
H
H
H
H
H
H
H
H
(bits 1 … 0)
(bits 7 … 0)
(bits 7 … 4)
(bits 3 … 0)
(bits 7 … 6)
(bits 5 … 4)
(bits 3 … 2)
PEB 2055
PEF 2055