PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 237

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

of 0C
W:MFSAR
W:CMDR
R:STAR
W:MFFIFO
W:MFFIFO
W:CMDR
R:ISTA
W:MFSAR
W:CMDR
R:STAR
W:MFFIFO
W:MFFIFO
W:CMDR
R:ISTA
W:MFSAR
W:CMDR
R:STAR
W:MFFIFO
W:MFFIFO
W:CMDR
R:ISTA
W:MFSAR
W:CMDR
R:STAR
W:MFFIFO
W:MFFIFO
W:CMDR
R:ISTA
If the D-channel access procedure is programmed, the IDEC MODE registers must
additionally be programmed accordingly i.e. for each channel MODE = 2C
Example
In a first step, the QUAT-S in IOM port 0, ch. 0 … 3 is programmed via the IOM-2 monitor
handler to the LT-T mode:
W:OMDR
Semiconductor Group
H
).
= EE
= 04
= 01
= 25
= 81
= 41
= 04
= 20
= 0C
= 01
= 25
= 81
= 01
= 04
= 20
= 14
= 01
= 25
= 81
= 01
= 04
= 20
= 1C
= 01
= 25
= 81
= 01
= 04
= 20
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
; activation ELIC with handshake protocol enabled
; monitor address of IOM port 0, channel 0
; reset MFFIFO
; MFFIFO write access enabled
; select QUAT-S Configuration Register
; set LT-T mode, output CLK1
; transmit MFFIFO content
; MFFI interrupt
; monitor address of IOM port 0, channel 1
; reset MFFIFO
; MFFIFO write access enabled
; select QUAT-S Configuration Register
; set LT-T mode
; transmit MFFIFO content
; MFFI interrupt
; monitor address of IOM port 0, channel 2
; reset MFFIFO
; MFFIFO write access enabled
; select QUAT-S Configuration Register
; set LT-T mode
; transmit MFFIFO content
; MFFI interrupt
; monitor address of IOM port 0, channel 3
; reset MFFIFO
; MFFIFO write access enabled
; select QUAT-S Configuration Register
; set LT-T mode
; transmit MFFIFO content
; MFFI interrupt
237
Application Hints
PEB 2055
PEF 2055
H
(instead