PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 55

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PEF2054NV21XT

Manufacturer Part Number
PEF2054NV21XT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF2054NV21XT

Lead Free Status / Rohs Status
Compliant
Access in multiplexed P-interface mode:
FC2..0
4.2.2.2 Configurable Interface Mode Register 2 (CMD2)
Access in demultiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
FC2
Framing output Control.
Given that CMD1:CSS = 0, these bits determine the position of the FSC
pulse relative to the CFI frame, as well as the type of FSC pulse generated.
The position and width of the FSC signal with respect to the CFI frame can
be found in the following two figures 20 and 21.
FC1
H
FC0
COC
55
CXF
read/write
read/write
Detailed Register Description
CRR
address: 7
OMDR:RBS = 1
address: 2E
CBN9
PEB 2055
PEF 2055
H
bit 0
H
CBN8

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