PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 73

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

Access in multiplexed P-interface mode:
Access in multiplexed P-interface mode:
The 9 byte deep CIFIFO stores the addresses of CFI time slots in which a C/I and/or a
SIG value change has taken place. This address information can then be used to read
the actual C/I or SIG value from the control memory.
SBV
SAD6..0
4.2.5.3 Monitor/Feature Control Channel FIFO (MFFIFO)
Access in demultiplexed P-interface mode:
Reset value: empty
The 16-byte bi-directional MFFIFO provides intermediate storage for data bytes to be
transmitted or received over the monitor or feature control channel.
MFD7..0
Note: The byte n + 1 of an n-byte transmit message in monitor channel is not defined.
4.2.6
4.2.6.1 Signaling FIFO (CIFIFO)
Access in demultiplexed P-interface mode:
Reset value: 0xxxxxxx
Semiconductor Group
bit 7
bit 7
MFD7
SBV
Status/Control Registers
MF Data bits 7..0; MFD7 (MSB) is the first bit to be sent over the serial CFI,
MFD0 (LSB) the last.
Signaling Byte Valid.
0… the SAD6..0 bits are invalid.
1… the SAD6..0 bits indicate a valid subscriber address. The polarity of SBV
Subscriber Address bits 6..0; The CM address which corresponds to the CFI
time slot where a C/I or SIG value change has taken place is encoded in
these bits. For C/I channels SAD6..0 point to an even CM-address (C/I
value), for SIG channels SAD6..0 point to an odd CM-address (stable SIG
value).
MFD6
SAD6
is chosen such that the whole 8 bits of the CIFIFO can be copied to the
MAAR register in order to read the upstream C/I or SIG value from the
control memory.
B
MFD5
SAD5
MFD4
SAD4
73
MFD3
SAD3
read/write
read/write
read
read
Detailed Register Description
MFD2
SAD2
address: B
OMDR:RBS = 0
address: 16
address: C
OMDR:RBS = 0
address: 18
MFD1
SAD1
PEB 2055
PEF 2055
H
H
bit 0
bit 0
H
H
MFD0
SAD0