PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 33

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

request can be determined by reading the ISTA register.
The INT-output is level active. It remains active until all interrupt sources have been
active. However, for the duration of a write access to the MASK-register the INT line is
deactivated. When using an edge-triggered interrupt controller, it is thus recommended
to rewrite the MASK-register at the end of any interrupt service routine.
Every interrupt source can be selectively masked by setting the respective bit of the
MASK register. Such masked interrupts will not be indicated in the ISTA register, nor will
they activate the INT line.
3.2
To operate properly, the EPIC always requires a PDC-clock.
To synchronize the PCM side, the EPIC should normally also be provided with a PFS
strobe. In most applications, the DCL and FSC will be output signals of the EPIC, derived
from the PDC via prescalers.
If the required CFI data rate cannot be derived from the PDC, DCL and FSC can also be
programmed as input signals. This is achieved by setting the EPIC CMD1:CSS-bit.
Frequency and phase of DCL and FSC may then be chosen almost independently of the
frequency and phase of PDC and PFS. However, the CFI clock source must still be
synchronous to the PCM-interface clock source; i.e. the clock source for the CFI
interface and the clock source for the PCM-interface must be derived from the same
master clock.
Chapter 5.2.2 provides further details on clocking.
3.3
A reset pulse of at least 4 PDC clock cycles has to be applied at the RES pin. The reset
pulse sets all registers to their reset values described in section 4.
The EPIC is now in CM reset mode (refer to 4.2.6.7). As the hardware reset does not
affect the EPIC memories CM and DM, a “software reset” of the CM has to be performed.
Subsequently the EPIC can be programmed to CM initialization, normal operation or test
mode.
During reset the address latch enable pin ALE is evaluated to determine the bus
interface type.
Interrupts
An interrupt of the EPIC is indicated by activating the INT line. The detailed cause of the
serviced. If a new status bit is set while an interrupt is being serviced, the INT remains
Semiconductor Group
Clocking
Reset
33
Operational Description
PEB 2055
PEF 2055