EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 102

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Stratix IV Device Handbook Volume 1
Two-Multiplier Adder Sum Mode
1
In a two-multiplier adder configuration, the DSP block can implement four 18-bit
two-multiplier adders (2 two-multiplier adders per half DSP block). You can
configure the adders to take the sum or difference of two multiplier outputs. You must
select summation or subtraction at compile time. The two-multiplier adder function
is useful for applications such as FFTs, complex FIR, and IIR filters.
page 4–23
Loopback mode is the other sub-feature of the two-multiplier adder mode.
Figure 4–15 on page 4–24
mode takes the 36-bit summation result of the two multipliers and feeds back the
most significant 18-bits to the input. The lower 18-bits are discarded. You have the
option to disable or zero-out the loopback data by using the dynamic zero_loopback
signal. A logic 1 value on the zero_loopback signal selects the zeroed data or
disables the looped back data, while a logic 0 selects the looped back data.
You must select the option to use loopback mode or the general two-multiplier adder
mode at compile time.
For two-multiplier adder mode, if all the inputs are full 18-bit and unsigned, the result
requires 37 bits. As the output data width in two-multiplier adder mode is limited to
36 bits, this 37-bit output requirement is not allowed. Any other combination that
does not violate the 36-bit maximum result is permitted; for example, two 16 × 16
signed two-multiplier adders is valid.
Two-multiplier adder mode supports the rounding and saturation logic unit. You can
use the pipeline registers and output registers within the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
shows the DSP block configured in two-multiplier adder mode.
shows the DSP block configured in the loopback mode. This
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
February 2011 Altera Corporation
Figure 4–14 on