EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 51
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
Figure 2–12. LUT Register from Two Combinational Blocks
February 2011 Altera Corporation
datain(datac)
aclr
sclr
clk
Similar to the carry chains, the top and bottom halves of shared arithmetic chains in
alternate LAB columns can be bypassed. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in an LAB while leaving the other half
available for narrower fan-in functionality. Every other LAB column is top-half
by-passable, while the other LAB columns are bottom-half by-passable.
For more information about the shared arithmetic chain interconnect, refer to
Interconnects” on page
LUT-Register Mode
LUT-register mode allows third-register capability within an ALM. Two internal
feedback loops allow combinational ALUT1 to implement the master latch and
combinational ALUT0 to implement the slave latch needed for the third register. The
LUT register shares its clock, clock enable, and asynchronous clear sources with the
top dedicated register.
combinational blocks within the ALM.
Figure 2–12
2–18.
shows the register constructed using two
4-input
5-input
LUT
LUT
combout
combout
sumout
sumout
Stratix IV Device Handbook Volume 1
LUT regout
“ALM
2–15
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