EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 31
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
Table 1–7. Stratix IV GT Device Features (Part 2 of 2)
February 2011 Altera Corporation
Feature
10G Transceiver
Channels
(600 Mbps - 11.3 Gbps
with PMA + PCS)
8G Transceiver
Channels
(600 Mbps - 8.5 Gbps
with PMA + PCS)
PMA-only CMU
Channels
(600 Mbps- 6.5 Gbps)
PCIe hard IP Blocks
High-Speed LVDS
SERDES
(up to 1.6 Gbps)
SP1-4.2 Links
M9K Blocks
(256 × 36 bits)
M144K Blocks
(2048 × 72 bits)
Total Memory (MLAB +
M9K + M144K) Kbits
Embedded Multipliers
18 × 18
PLLs
User I/Os (4),
Speed Grade
(fastest to slowest)
Notes to
(1) You can configure all 10G transceiver channels as 8G transceiver channels. For example, the EP4S40G2F40 device has twenty-four 8G
(2) Total pairs of high-speed LVDS SERDES take the lowest channel count of R
(3) Four multiplier adder mode.
(4) The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver
(5) This data is preliminary.
transceiver channels and the EP4S100G5F45 device has thirty-two 8G transceiver channels.
pins and dedicated configuration pins are not included in the pin count.
Table
(3)
1–7:
(5)
(2)
(1)
EP4S40G2
–1, –2, –3
17,133
1,235
1,288
654
12
12
12
46
22
2
2
8
EP4S40G5
–1, –2, –3
27,376
1,280
1,024
654
12
12
12
46
64
2
2
8
EP4S100G2
–1, –2, –3
17,133
1,235
1,288
654
24
12
46
22
0
2
2
8
X
/T
X
.
EP4S100G3
–1, –2, –3
17,248
936
832
781
24
16
47
36
12
8
4
2
EP4S100G4
–1, –2, –3
22,564
1,248
1,024
781
24
16
47
48
12
8
4
2
Stratix IV Device Handbook Volume 1
–1, –2, –3 –1, –2, –3
654
24
12
46
0
2
2
8
EP4S100G5
27,376
1,280
1,024
64
781
32
16
47
12
0
4
2
1–17
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