EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 374

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–40
Device Configuration Pins
Table 10–9. Stratix IV Configuration Pin Summary (Part 1 of 2)
Stratix IV Device Handbook Volume 1
TDI
TMS
TCK
TRST
TDO
CRC_ERROR
Jam STAPL
Description
f
Figure 10–18
Figure 10–18. JTAG Configuration of a Single Device Using a Microprocessor
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain.
(2) Connect the nCONFIG and MSEL[2..0] pins to support a non-JTAG configuration scheme. If you use only a JTAG
(3) Connect nCE to GND or drive it low for successful JTAG configuration.
(4) The microprocessor must use the same I/O standard as V
Jam™ STAPL, JEDEC standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or configuration
of programmable devices and testing of electronic systems, using the IEEE 1149.1
JTAG interface. Jam STAPL is a freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP
state machine.
For more information about JTAG and Jam STAPL in embedded environments, refer
to
visit the Altera website at www.altera.com.
The following tables list the connections and functionality of all the
configuration-related pins on Stratix IV devices.
configuration pins and their power supply.
Using Jam STAPL for ISP via an Embedded
V
configuration, connect nCONFIG to V
convenient on your board.
CCPGM
Figure
must be high enough to meet the V
10–18:
Input/Output
shows JTAG configuration of a Stratix IV device using a microprocessor.
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Output
Output
Input
Input
Input
Input
Microprocessor
ADDR
Memory
DATA
CCGPM
Dedicated
IH
Yes
Yes
Yes
Yes
Yes
and MSEL[2..0] to GND. Pull DCLK either high or low, whichever is
—
V CCPD
specification of the I/O on the device.
(Note 1)
TRST
TDI (4)
TCK (4)
TMS (4)
TDO (4)
Stratix IV Device
Processor. To download the Jam Player,
CCPD
CONF_DONE
to drive the JTAG pins.
Table 10–9
Powered By
MSEL[2..0]
nSTATUS
nCONFIG
Pull-up
(3) nCE
V
V
V
V
V
DCLK
nCEO
CCPD
CCPD
CCPD
CCPD
CCPD
V CCPGM (1)
(2)
(2)
(2)
N.C.
GND
lists the Stratix IV
10 kΩ
V CCPGM (1)
April 2011 Altera Corporation
Configuration Mode
Optional, all modes
10 kΩ
Device Configuration Pins
JTAG
JTAG
JTAG
JTAG
JTAG