EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 161
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Table 5–10. Real-Time PLL Reconfiguration Ports
February 2011 Altera Corporation
scandata
scanclk
scanclkena
configupdate
scandone
scandataout
PLL Port Name
Table 5–10
To reconfigure the PLL counters, follow these steps:
1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in the
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
3. After all 234 bits (top and bottom PLLs) or 180 bits (left and right PLLs) have been
4. The configupdate signal is asserted for one scanclk cycle to update the PLL
5. The scandone signal goes high, indicating the PLL is being reconfigured. A falling
6. Reset the PLL using the areset signal if you make any changes to the M, N, or
7. You can repeat steps 1-5 to reconfigure the PLL any number of times.
Serial input data stream to scan
chain.
Serial clock input signal. This clock
can be free running.
Enables scanclk and allows the
scandata to be loaded in the scan
chain. Active high.
Writes the data in the scan chain to
the PLL. Active high.
Indicates when the PLL has finished
reprogramming. A rising edge
indicates the PLL has begun
reprogramming. A falling edge
indicates the PLL has finished
reprogramming.
Used to output the contents of the
scan chain.
first bit of scandata (D0).
scanclk.
scanned into the scan chain, the scanclkena signal is de-asserted to prevent
inadvertent shifting of bits in the scan chain.
counters with the contents of the scan chain.
edge indicates the PLL counters have been updated with new settings.
post-scale output C counters or to the Icp, R, or C settings.
lists how these signals can be driven by the PLD logic array or I/O pins.
Description
Logic array or I/O pin
GCLK, RCLK or I/O pins
Logic array or I/O pin
Logic array or I/O pin
PLL reconfiguration circuit
PLL reconfiguration circuit
Source
Stratix IV Device Handbook Volume 1
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
Logic array or I/O pins
Logic array or I/O pins
Destination
5–45
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