EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 113
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Figure 4–21. Rounding and Saturation Locations
February 2011 Altera Corporation
16 User defined SAT Positions (bit 43-28)
43
43
1
1
1
42
42
Two saturation modes are supported in Stratix IV:
■
■
You must select one of the two options at compile time.
In 2’s-complement format, the maximum negative number that can be represented is
–2
the maximum negative number to –2
■
■
Table 4–8
36-bits.
Table 4–8. Examples of Saturation
Stratix IV devices have up to 16 configurable bit positions out of the 44-bit bus
([43:0]) for the rounding and saturate logic unit, providing higher flexibility. These
16-bit positions are located at bits [21:6] for rounding and [43:28] for saturation, as
shown in
You must select the 16 configurable bit positions at compile time.
For symmetric saturation, the RND bit position is also used to determine where the
LSP for the saturated data is located.
(n –1)
Asymmetric saturation mode
Symmetric saturation mode
Asymmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000000
Symmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000001
44- to 36-Bits Saturation
, while the maximum positive number is 2
5926AC01342h
ADA38D2210h
lists how saturation works. In this example, a 44-bit input is saturated to
Figure
29
4–21.
28
16 User defined RND Positions (bit 21-6)
21
20
Symmetric SAT Result
800000001h
(n–1)
7FFFFFFFFh
+ 1. For example, for 32 bits:
(n–1)
– 1. Symmetrical saturation limits
7
6
Stratix IV Device Handbook Volume 1
Asymmetric SAT Result
800000000h
7FFFFFFFFh
1
0
0
4–33
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