EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 72
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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3–16
Clocking Modes
Table 3–9. TriMatrix Memory Clock Modes
Stratix IV Device Handbook Volume 1
Independent
Input/output
Read/write
Single clock
Clocking Mode
ROM Mode
FIFO Mode
f
1
c
All Stratix IV TriMatrix memory blocks support ROM mode. A .mif file initializes the
ROM contents of these blocks. The address lines of the ROM are registered on M9K
and M144K blocks, but can be unregistered on MLABs. The outputs can be registered
or unregistered. Output registers can be asynchronously cleared. The ROM read
operation is identical to the read operation in the single-port RAM configuration.
All TriMatrix memory blocks support FIFO mode. MLABs are ideal for designs with
many small, shallow FIFO buffers. To implement FIFO buffers in your design, use the
Quartus II software FIFO MegaWizard Plug-In Manager. Both single- and dual-clock
(asynchronous) FIFO buffers are supported.
For more information about implementing FIFO buffers, refer to the
DCFIFO Megafunctions User
MLABs do not support mixed-width FIFO mode.
Stratix IV TriMatrix memory blocks support the following clocking modes:
■
■
■
■
Violating the setup or hold time on the memory block address registers could corrupt
memory contents. This applies to both read and write operations.
Table 3–9
Dual-Port Mode
“Independent Clock Mode” on page 3–17
“Input/Output Clock Mode” on page 3–17
“Read/Write Clock Mode” on page 3–17
“Single Clock Mode” on page 3–17
True
v
v
v
—
lists which clocking mode/memory mode combinations are supported.
Dual-Port Mode
Simple
v
v
v
—
Guide.
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Single-Port Mode
v
v
—
—
ROM Mode
February 2011 Altera Corporation
v
v
v
—
SCFIFO and
FIFO Mode
Clocking Modes
v
v
—
—
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