EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 115
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 4: DSP Blocks in Stratix IV Devices
Software Support
Table 4–9. DSP Block Dynamic Signals (Part 2 of 2)
Software Support
February 2011 Altera Corporation
accum_sload
zero_chainout
zero_loopback
rotate
shift_right
Total Signals per Half Block
clock0
clock1
clock2
clock3
ena0
ena1
ena2
ena3
aclr0
aclr1
aclr2
aclr3
Total Count per Full Block
Signal Name
f
Altera provides two distinct methods for implementing various modes of the DSP
block in a design—instantiation and inference. Both methods use the following
Quartus II megafunctions:
■
■
■
■
To use the DSP block, instantiate the megafunctions in the Quartus II software.
Alternatively, with inference, create an HDL design and synthesize it using a
third-party synthesis tool (such as LeonardoSpectrum™, Synplify, or Quartus II
Native Synthesis) that infers the appropriate megafunction by recognizing
multipliers, multiplier adders, multiplier accumulators, and shift functions. Using
either method, the Quartus II software maps the functionality to the DSP blocks
during compilation.
For instructions about using these megafunctions and the MegaWizard Plug-In
Manager, refer to Quartus II software Help.
lpm_mult
altmult_add
altmult_accum
altfp_mult
Dynamically specifies whether the accumulator value is zero.
■
■
Dynamically specifies whether the chainout value is zero.
Dynamically specifies whether the loopback value is zero.
rotate = 1, the rotation feature is enabled
shift_right = 1, the shift right feature is enabled
DSP-block-wide clock signals.
Input and Pipeline Register enable signals.
DSP block-wide asynchronous clear signals (active low).
accum_sload = 0, accumulation input is from the output registers
accum_sload = 1, accumulation input is set to zero
Function
Stratix IV Device Handbook Volume 1
Count
11
34
1
1
1
1
1
4
4
4
4–35
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