EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 307
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Left and Right PLLs (PLL_Lx and PLL_Rx)
Figure 8–22. Phase Relationship for External PLL Interface Signals
Left and Right PLLs (PLL_Lx and PLL_Rx)
February 2011 Altera Corporation
(internal PLL clk)
phase shift)
phase shift)
phase shift)
Serial data
c0 (-180
VCO clk
c1 (288
c2 (-18
inclk0
f
D1
The
data are edge aligned. Introducing a phase shift of –180° to sampling clock (c0)
ensures that the input data is center-aligned with respect to the c0, as shown in
Figure
The Stratix IV device family contains up to eight left and right PLLs with up to four
PLLs located on the left side and four on the right side of the device. The left PLLs can
support high-speed differential I/O banks on the left side; the right PLLs can support
high-speed differential I/O banks on the right side of the device. The high-speed
differential I/O receiver and transmitter channels use these left and right PLLs to
generate the parallel clocks (rx_outclock and tx_outclock) and high-speed clocks
(diffioclk).
Figure 8–2 on page 8–3
right PLLs for Stratix IV E, GT, and GX devices. The PLL VCO operates at the clock
frequency of the data rate. Clock switchover and dynamic reconfiguration are allowed
using the left and right PLL in high-speed differential I/O support mode.
For more information, refer to the
Equation 8–1
8–22.
D2
D3
calculations for phase shift assume that the input clock and serial
and
D4
Figure 8–3 on page 8–4
D5
Clock Network and PLLs in Stratix IV Devices
D6
D7
show the locations of the left and
D8
Stratix IV Device Handbook Volume 1
D9
D10
chapter.
8–29
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