EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 57
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
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SIV51003-3.2
Overview
Table 3–1. Summary of TriMatrix Memory Features (Part 1 of 2)
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51003-3.2
Maximum performance
Total RAM bits
(including parity bits)
Configurations
(depth × width)
Parity bits
Feature
This chapter describes the TriMatrix embedded memory blocks in Stratix
TriMatrix embedded memory blocks provide three different sizes of embedded
SRAM to efficiently address the needs of Stratix IV FPGA designs. TriMatrix memory
includes 640-bit memory logic array blocks (MLABs), 9-Kbit M9K blocks, and
144-Kbit M144K blocks. MLABs have been optimized to implement filter delay lines,
small FIFO buffers, and shift registers. You can use the M9K blocks for general
purpose memory applications and the M144K blocks for processor code storage,
packet buffering, and video frame buffering.
You can independently configure each embedded memory block to be a single- or
dual-port RAM, FIFO buffer, ROM, or shift register using the Quartus
MegaWizard™ Plug-In Manager. You can stitch together multiple blocks of the same
type to produce larger memories with minimal timing penalty. TriMatrix memory
provides up to 31,491 Kbits of embedded SRAM at up to 600 MHz operation.
This chapter contains the following sections:
■
■
■
■
Table 3–1
“Overview”
“Memory Modes” on page 3–8
“Clocking Modes” on page 3–16
“Design Considerations” on page 3–17
lists the features supported by the three sizes of TriMatrix memory.
600 MHz
64 × 10
32 × 16
32 × 18
32 × 20
MLABs
64 × 8
64 × 9
640
v
3. TriMatrix Embedded Memory Blocks in
M9K Blocks
600 MHz
512 × 16
512 × 18
256 × 32
256 × 36
8K × 1
4K × 2
2K × 4
1K × 8
1K × 9
9216
v
Stratix IV Devices
M144K Blocks
540 MHz
147,456
16K × 8
16K × 9
8K × 16
8K × 18
4K × 32
4K × 36
2K × 64
2K × 72
®
v
II
®
IV devices.
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