EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 274
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
- Current page: 274 of 432
- Download datasheet (11Mb)
7–54
Stratix IV Device Handbook Volume 1
Figure 7–34
Figure 7–34. Delay Chains in an I/O Block
Each DQS logic block contains a delay chain after the dqsbusout output and another
delay chain before the dqsenable input.
DQS input path.
Figure 7–35. Delay Chains in the DQS Input Path
octdelaysetting2 (only)
octdelaysetting1 (only)
DQS
shows the delay chains in an I/O block.
rtena
D5 OCT
Delay
Chain
D6 OCT
Delay
Chain
DQS
Delay
Chain
(outputdelaysetting2 + outputfinedelaysetting2) or
(outputonlydelaysetting2 + outputonlyfinedelaysetting2)
D6 Output-
Enable Delay
Chain
D5 Output-
Enable Delay
Chain
(dqsenabledelaysetting +
dqsenablefinedelaysetting)
oe
Figure 7–35
Chapter 7: External Memory Interfaces in Stratix IV Devices
(dqsbusoutdelaysetting +
dqsbusoutfinedelaysetting)
(padtoinputregisterdelaysetting +
padtoinputregisterfinedelaysetting)
D4 Delay
Chain
(outputdelaysetting2 +
outputfinedelaysetting2)
D6 Delay
Delay
Chain
D1 Delay
Delay Chain
shows the delay chains in the
Stratix IV External Memory Interface Features
(outputdelaysetting1 +
outputfinedelaysetting1)
dqsenable
dqsin
Enable
Control
Enable
D5 Delay
Delay
Chain
DQS
DQS
T11 Delay
Chain
February 2011 Altera Corporation
0
1
dqsbusout
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