EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 202
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
- Current page: 202 of 432
- Download datasheet (11Mb)
6–30
Figure 6–21. Dynamic Parallel OCT in Stratix IV Devices
Stratix IV Device Handbook Volume 1
Receiver
f
1
50 Ω
50
Transmitter
50 Ω
Stratix IV OCT
When using calibrated input parallel and calibrated output series termination on
bidirectional pins, they must use the same termination value because each I/O pin
can only reference one OCT calibration block. The only exception is when using 50 Ω
parallel OCT and 25 Ω series OCT using the left shift series termination control. For
example, you cannot use calibrated 50 Ω parallel OCT on the input buffer of a
bidirectional pin and calibrated 40 Ω series OCT on the output buffer because these
would require two separate calibration blocks with different RUP and RDN resistor
values.
For more information about tolerance specifications for OCT with calibration, refer to
the
Stratix IV OCT
DC and Switching Characteristics for Stratix IV Devices
VCCIO
VCCIO
GND
GND
100 Ω
100 Ω
100 Ω
100
100 Ω
100
Z
Z
O
O
= 50 Ω
= 50 Ω
On-Chip Termination Support and I/O Termination Schemes
100 Ω
100 Ω
100 Ω
100 Ω
100 Ω
100
100 Ω
100
VCCIO
VCCIO
GND
GND
Stratix IV OCT
Stratix IV OCT
Chapter 6: I/O Features in Stratix IV Devices
chapter.
Transmitter
February 2011 Altera Corporation
Receiver
50 Ω
50 Ω
50
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