EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 375
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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- Download datasheet (11Mb)
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Device Configuration Pins
Table 10–9. Stratix IV Configuration Pin Summary (Part 2 of 2)
April 2011 Altera Corporation
DATA0
DATA[7..1]
INIT_DONE
CLKUSR
nSTATUS
nCE
CONF_DONE
nCONFIG
PORSEL
ASDO
nCSO
DCLK
nIO_PULLUP
nCEO
MSEL[2..0]
Notes to
(1) The total number of pins is 29. The total number of dedicated pins is 18.
(2) Although MSEL[2..0], PORSEL, and nIO_PULLUP are powered up by V
(3) These pins are powered up by V
(4) To tri-state this pin, in the Quartus II software, on the Assignments menu, select Device. On the Device page, select Device and Pin Options...
without using a pull-up or pull-down resistor.
On the Device and Pin Options page, select Configuration and select the Enable input tri-state on active configuration pins in user mode
option.
(4)
(4)
(4)
Table
Description
10–9:
CCPGM
during configuration. These pins are powered up by V
Input/Output
Bidirectional
Bidirectional
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Dedicated
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CC
—
—
—
—
, Altera recommends connecting these pins to V
(Note 1)
V
V
V
V
V
CCPGM
CCPGM
CCPGM/
Powered By
CCPGM
CCPGM
CCIO
V
V
V
Pull-up
V
V
V
V
V
V
V
CC
CC
CC
CCPGM
CCPGM
CCPGM
CCPGM
CCPGM
CCPGM
CCPGM
/V
/V
if they are used as regular I/O in user mode.
V
/Pull-up
/Pull-up
CCIO
CCIO
CCIO
(2)
(2)
(2)
(3)
(3)
(3)
Stratix IV Device Handbook Volume 1
All modes except JTAG
Configuration Mode
Optional, all modes
CCPGM
All modes
All modes
All modes
All modes
All modes
All modes
All modes
All modes
Optional
PS, FPP
FPP
AS
AS
AS
or GND directly
10–41
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