EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 353
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Active Serial Configuration (Serial Configuration Devices)
April 2011 Altera Corporation
1
1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
When the Stratix IV device is in user mode, you can initiate reconfiguration by pulling
the nCONFIG pin low. The nCONFIG pin must be low for at least 2 μs. When nCONFIG is
pulled low, the device also pulls nSTATUS and CONF_DONE low and all I/O pins are
tri-stated. After nCONFIG returns to a logic high level and nSTATUS is released by the
Stratix IV device, reconfiguration begins.
If you wish to gain control of the EPCS pins, hold the nCONFIG pin low and pull the
nCE pin high. This causes the device to reset and tri-state the AS configuration pins.
The timing parameters for AS mode are not listed here because the t
t
for PS mode listed in
You can configure multiple Stratix IV devices using a single serial configuration
device. You can cascade multiple Stratix IV devices using the chip-enable (nCE) and
chip-enable-out (nCEO) pins. The first device in the chain must have its nCE pin
connected to GND. You must connect its nCEO pin to the nCE pin of the next device in
the chain. When the first device captures all of its configuration data from the
bitstream, it drives the nCEO pin low, enabling the next device in the chain. You must
leave the nCEO pin of the last device unconnected. The nCONFIG, nSTATUS, CONF_DONE,
DCLK, and DATA0 pins of each device in the chain are connected (refer to
The first Stratix IV device in the chain is the configuration master and controls
configuration of the entire chain. You must connect its MSEL pins to select the AS
configuration scheme. The remaining Stratix IV devices are configuration slaves. You
must connect their MSEL pins to select the PS configuration scheme. Any other Altera
device that supports PS configuration can also be part of the chain as a configuration
slave.
STATUS
, t
CF2ST1
, and t
CD2UM
Table 10–7 on page
timing parameters are identical to the timing parameters
10–30.
Stratix IV Device Handbook Volume 1
STATUS
CF2CD
specification.
Figure
, t
CF2ST0
10–7).
, t
10–19
CFG
,
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