EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 53
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
Figure 2–14. Register Chain within the LAB
Note to
(1) You can use the combinational or adder logic to implement an unrelated, un-registered function.
February 2011 Altera Corporation
Figure
Register Chain
2–14:
In addition to general routing outputs, ALMs in the LAB have register-chain outputs.
Register-chain routing allows registers in the same LAB to be cascaded together. The
register-chain interconnect allows the LAB to use LUTs for a single combinational
function and the registers to be used for an unrelated shift-register implementation.
These resources speed up connections between ALMs while saving local interconnect
resources (refer to
advantage of these resources to improve utilization and performance.
For more information about the register chain interconnect, refer to
Interconnects” on page
Combinational
Combinational
Logic
Logic
Figure
(Note 1)
adder0
adder1
adder0
adder1
2–18.
2–14). The Quartus II Compiler automatically takes
reg_chain_out
reg_chain_in
labclk
D
D
D
D
reg0
reg1
reg0
reg1
From previous ALM
within the LAB
To next ALM
within the LAB
Q
Q
Q
Q
To general or
To general or
To general or
To general or
To general or
To general or
To general or
To general or
Stratix IV Device Handbook Volume 1
local routing
local routing
local routing
local routing
local routing
local routing
local routing
local routing
“ALM
2–17
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