EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 280

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–2
Figure 8–1. I/O Bank Support in the Stratix IV Device Family
Notes to
(1) Column input buffers are true LVDS buffers, but do not support 100-Ω differential on-chip termination.
(2) Column output buffers are single ended and need external termination schemes to support LVDS, mini-LVDS, and RSDS standards. For more
(3) Row input buffers are true LVDS buffers and support 100-Ω differential on-chip termination.
(4) Row output buffers are true LVDS buffers.
Stratix IV Device Handbook Volume 1
information, refer to the
Figure
with 'Use External PLL'
Option Enabled
LVDS Interface
8–1:
■
■
■
■
For high-speed differential interfaces, the Stratix IV device family supports the
following differential I/O standards:
■
■
■
In the Stratix IV device family, I/Os are divided into row and column I/Os.
shows I/O bank support for the Stratix IV device family. The row I/Os provide
dedicated SERDES circuitry.
I/O Features in Stratix IV Devices
Data realignment
DPA
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs) (located on left and right sides of the device)
LVDS
Mini-LVDS
Reduced swing differential signaling (RSDS)
SERDES Circuitry (3), (4)
Row I/Os with
Dedicated
chapter.
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
with 'Use External PLL'
Option Disabled
LVDS Interface
(Note
LVDS I/Os
1), (2), (3),
(4)
February 2011 Altera Corporation
Column I/Os (1), (2)
Figure 8–1
Overview