EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 38

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–2
Figure 2–1. Stratix IV LAB Structure and Interconnects
Stratix IV Device Handbook Volume 1
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
R20
R4
Figure 2–1
The LAB of the Stratix IV device has a derivative called memory LAB (MLAB), which
adds look-up table (LUT)-based SRAM capability to the LAB, as shown in
The MLAB supports a maximum of 640 bits of simple dual-port static random access
memory (SRAM). You can configure each ALM in an MLAB as either a 64 × 1 or a
32 × 2 block, resulting in a configuration of either a 64 × 10 or a 32 × 20 simple
dual-port SRAM block. MLAB and LAB blocks always coexist as pairs in all Stratix IV
families. MLAB is a superset of the LAB and includes all LAB features.
Local Interconnect
shows the Stratix IV LAB structure and interconnects.
LAB
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
C4
from Either Side by Columns & LABs,
C12
Local Interconnect is Driven
& from Above by Rows
Row Interconnects of
Variable Speed & Length
MLAB
ALMs
Column Interconnects of
Variable Speed & Length
February 2011 Altera Corporation
Logic Array Blocks
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Figure
2–2.