EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 208
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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6–36
Stratix IV Device Handbook Volume 1
1
User Mode
In user mode, the OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER[9..0] signals are used to
calibrate and serially transfer calibration codes from each OCT calibration block to
any I/O.
descriptions.
Table 6–12. OCT Calibration Block Ports for User Control
Figure 6–24
blocks are in calibration mode; when ENAOCT is 0, all OCT calibration blocks are in
serial data transfer mode. The OCTUSRCLK clock frequency must be 20 MHz or less.
You must generate all user signals on the rising edge of OCTUSRCLK.
Figure 6–24
Figure 6–24. Signals Used for User Mode Calibration
OCTUSRCLK
ENAOCT
ENASER[9..0]
S2PENA_<bank#>
nCLRUSR
Signal Name
Table 6–12
shows the flow of the user signal. When ENAOCT is 1, all OCT calibration
does not show transceiver banks and transceiver calibration blocks.
Bank 1A
Bank 1B
Bank 1C
Bank 2C
Bank 2B
Bank 2A
lists the user-controlled calibration block signal names and their
Clock for OCT block.
Enable OCT Termination (Generated by user IP).
When ENOCT = 0, each signal enables the OCT serializer for the
corresponding OCT calibration block.
When ENAOCT = 1, each signal enables OCT calibration for the
corresponding OCT calibration block.
Serial-to-parallel load enable per I/O bank.
Clear user.
CB1
CB0
CB9
CB2
S2PENA_1C
OCTUSRCLK,
ENASER[N]
CB8
CB3
Stratix IV
ENAOCT, nCLRUSR,
Core
S2PENA_4C
Description
S2PENA_6C
Chapter 6: I/O Features in Stratix IV Devices
CB4
CB7
CB6
CB5
February 2011 Altera Corporation
Bank 6A
Bank 6B
Bank 6C
Bank 5C
Bank 5B
Bank 5A
OCT Calibration
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