EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 371
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
JTAG Configuration
April 2011 Altera Corporation
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon completion. At
the end of configuration, the software checks the state of CONF_DONE through the JTAG
port. When the Quartus II software generates a JAM file (.jam) for a multi-device
chain, it contains instructions so that all the devices in the chain are initialized at the
same time. If CONF_DONE is not high, the Quartus II software indicates that
configuration has failed. If CONF_DONE is high, the software indicates that
configuration was successful. After the configuration bitstream is transmitted serially
using the JTAG TDI port, the TCK port is clocked an additional 1,094 cycles to perform
device initialization.
Stratix IV devices have dedicated JTAG pins that always function as JTAG pins. Not
only can you perform JTAG testing on Stratix IV devices before and after, but also
during configuration. While other device families do not support JTAG testing during
configuration, Stratix IV devices support the bypass, ID code, and sample instructions
during configuration without interrupting configuration. All other JTAG instructions
may only be issued by first interrupting configuration and reprogramming the I/O
pins using the CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured using the JTAG port
and when issued, interrupts configuration. This instruction allows you to perform
board-level testing prior to configuring the Stratix IV device or waiting for a
configuration device to complete configuration. After configuration has been
interrupted and JTAG testing is complete, you must reconfigure the part using JTAG
(PULSE_CONFIG instruction) or by pulsing nCONFIG low.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on
Stratix IV devices do not affect JTAG boundary-scan or programming operations.
Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration for Stratix IV devices, consider the
dedicated configuration pins.
JTAG configuration.
Table 10–8. Dedicated Configuration Pin Connections During JTAG Configuration (Part 1 of 2)
nCE
nCEO
MSEL
Signal
On all Stratix IV devices in the chain, nCE must be driven low by connecting it to
GND, pulling it low using a resistor, or driving it by some control circuitry. For
devices that are also in multi-device FPP, AS, or PS configuration chains, the nCE
pins must be connected to GND during JTAG configuration or JTAG must be
configured in the same order as the configuration chain.
On all Stratix IV devices in the chain, you can leave nCEO floating or connected to
the nCE of the next device.
Do not leave these pins floating. These pins support whichever non-JTAG
configuration is used in production. If you only use JTAG configuration, tie these
pins to GND.
Table 10–8
lists how these pins are connected during
Description
Stratix IV Device Handbook Volume 1
10–37
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