EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 213
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Figure 6–29. Differential SSTL I/O Standard Termination
February 2011 Altera Corporation
Termination
External
On-Board
Termination
OCT
Differential I/O Standards Termination
Differential SSTL Class I
Series OCT
Transmitter
Transmitter
1
50 Ω
Stratix IV devices support differential SSTL-18 and SSTL-2, differential HSTL-18,
HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS.
Figure 6–35
Differential HSTL and SSTL outputs are not true differential outputs. They use two
single-ended outputs with the second output programmed as inverted.
Differential SSTL Class I
25 Ω
25 Ω
Z
Z
50 Ω
50 Ω
0
0
= 50 Ω
= 50 Ω
50 Ω
V TT V TT
show the details of various differential I/O terminations on these devices.
V CCIO
50 Ω
100 Ω
GND
100 Ω
100 Ω
100 Ω
V CCIO
Receiver
Receiver
GND
Series OCT
Differential SSTL Class II
Transmitter
Transmitter
25 Ω
50 Ω
25 Ω
25 Ω
V TT V TT
V TT
V TT
Differential SSTL Class II
50 Ω
50 Ω
Z
Z
0
0
50 Ω
= 50 Ω
= 50 Ω
50 Ω
50 Ω
Stratix IV Device Handbook Volume 1
50 Ω
Figure 6–29
V CCIO
V TT V TT
100 Ω
GND
100 Ω
100 Ω
100 Ω
50 Ω
V CCIO
Receiver
GND
through
Receiver
6–41
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