EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 178
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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6–6
Figure 6–1. Stratix IV E Devices I/0 Banks
Notes to
(1) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
(2) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support.
(3) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(4) Column I/O supports PCI/PCI-X with on-chip clamp diode. Row I/O supports PCI/PCI-X with external clamp diode.
(5) Clock inputs on column I/Os are powered by V
(6) Row I/O supports the true LVDS output buffer.
(7) Column and row I/O banks support LVPECL standards for input clock operation.
(8)
Stratix IV Device Handbook Volume 1
inverted.
single-ended clock inputs. All outputs use the corresponding bank V
Figure 6–1
Figure
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
Bank 3A
6–1:
Bank 8A
I/O banks 3A, 3B, and 3C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
I/O banks 8A, 8B, and 8C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 3B
Bank 8B
SSTL-15 Class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15
Class II, differential HSTL-12 Class II standards are
only supported for input operations.
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I, and differential HSTL -12
Class I standards for input and output operations.
LVPECL I/O standard for input operation on dedicated
clock input pins.
CCCLKIN
(Note
Bank 3C
when configured as differential clock inputs. They are powered by V
Bank 8C
1), (2), (3), (4), (5), (6), (7),
CCIO
.
Bank 7C
Bank 4C
I/O banks 7A, 7B, and 7C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
I/O banks 4A, 4B, and 4C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 4B
(8)
Bank 7B
Chapter 6: I/O Features in Stratix IV Devices
February 2011 Altera Corporation
Bank 4A
Bank 7A
CCIO
when configured as
I/O Banks
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