EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 398
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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10–64
Design Security
Stratix IV Device Handbook Volume 1
1
This section provides an overview of the design security feature and its
implementation on Stratix IV devices using the advanced encryption standard (AES).
It also covers the new security modes available in Stratix IV devices.
As Stratix IV devices continue play a role in larger and more critical designs in
competitive commercial and military environments, it is increasingly important to
protect the designs from copying, reverse engineering, and tampering.
Stratix IV devices address these concerns with both volatile and non-volatile security
feature support. Stratix IV devices have the ability to decrypt configuration bitstreams
using the AES algorithm, an industry-standard encryption algorithm that is FIPS-197
certified. Stratix IV devices have a design security feature that utilizes a 256-bit
security key.
Stratix IV devices store configuration data in SRAM configuration cells during device
operation. Because SRAM is volatile, the SRAM cells must be loaded with
configuration data each time the device powers up. It is possible to intercept
configuration data when it is being transmitted from the memory source (flash
memory or a configuration device) to the device. The intercepted configuration data
could then be used to configure another device.
When using the Stratix IV design security feature, the security key is stored in the
Stratix IV device. Depending on the security mode, you can configure the Stratix IV
device using a configuration file that is encrypted with the same key, or for board
testing, configured with a normal configuration file.
The design security feature is available when configuring Stratix IV devices using FPP
configuration mode with an external host (such as a MAX II device or
microprocessor), or when using fast AS or PS configuration schemes. The design
security feature is also available in remote update with fast AS configuration mode.
The design security feature is not available when you are configuring your Stratix IV
device using JTAG-based configuration. For more information, refer to
Configuration Schemes” on page
When using a serial configuration scheme such as PS or fast AS, configuration time is
the same whether or not you enable the design security feature. If the FPP scheme is
used with the design security or decompression feature, a ×4 DCLK is required. This
results in a slower configuration time when compared with the configuration time of
a Stratix IV device that has neither the design security nor the decompression feature
enabled.
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
10–67.
April 2011 Altera Corporation
“Supported
Design Security
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