CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 13

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Power Control Register [0xC00A] [R/W]
Register Description
The Power Control register controls the power-down and
wakeup options. Either the sleep mode or the halt mode
options can be selected. All other writable bits in this register
can be used as a wakeup source while in sleep mode.
Host/Device 2 Wake Enable (Bit 14)
The Host/Device 2 Wake Enable bit enables or disables a
wakeup condition to occur on an Host/Device 2 transition. This
wake up from the SIE port does not cause an interrupt to the
on-chip CPU.
1: Enable wakeup on Host/Device 2 transition.
0: Disable wakeup on Host/Device 2 transition.
Host/Device 1 Wake Enable (Bit 12)
The Host/Device 1 Wake Enable bit enables or disables a
wakeup condition to occur on an Host/Device 1 transition. This
wakeup from the SIE port does not cause an interrupt to the
on-chip CPU.
1: Enable wakeup on Host/Device 1 transition
0: Disable wakeup on Host/Device 1 transition
OTG Wake Enable (Bit 11)
The OTG Wake Enable bit enables or disables a wakeup
condition to occur on either an OTG VBUS_Valid or OTG ID
transition (IRQ20).
1: Enable wakeup on OTG VBUS valid or OTG ID transition
0: Disable wakeup on OTG VBUS valid or OTG ID transition
HSS Wake Enable (Bit 9)
The HSS Wake Enable bit enables or disables a wakeup
condition to occur on an HSS Rx serial input transition. The
processor may take several hundreds of microseconds before
being operational after wakeup. Therefore, the incoming data
byte that causes the wakeup will be discarded.
1: Enable wakeup on HSS Rx serial input transition
0: Disable wakeup on HSS Rx serial input transition
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Wake Enable
Reserved
R/W
HPI
15
0
7
0
-
Host/Device 2
Wake Enable
R/W
14
0
6
0
-
Reserved
Reserved
Figure 11. Power Control Register
13
0
5
0
-
-
Host/Device 1
Wake Enable
Wake Enable
R/W
R/W
GPI
12
0
4
0
SPI Wake Enable (Bit 8)
The SPI Wake Enable bit enables or disables a wakeup
condition to occur on a falling SPI_nSS input transition. The
processor may take several hundreds of microseconds before
being operational after wakeup. Therefore, the incoming data
byte that causes the wakeup will be discarded.
1: Enable wakeup on falling SPI nSS input transition
0: Disable SPI_nSS interrupt
HPI Wake Enable (Bit 7)
The HPI Wake Enable bit enables or disables a wakeup
condition to occur on an HPI interface read.
1: Enable wakeup on HPI interface read
0: Disable wakeup on HPI interface read
GPI Wake Enable (Bit 4)
The GPI Wake Enable bit enables or disables a wakeup
condition to occur on a GPIO(25:24) transition.
1: Enable wakeup on GPIO(25:24) transition
0: Disable wakeup on GPIO(25:24) transition
Boost 3V OK (Bit 2)
The Boost 3V OK bit is a read only bit that returns the status
of the OTG Boost circuit.
1: Boost circuit not ok and internal voltage rails are below 3.0V
0: Boost circuit ok and internal voltage rails are at or above
3.0V
Sleep Enable (Bit 1)
Setting this bit to ‘1’ immediately initiates SLEEP mode. While
in SLEEP mode, the entire chip is paused achieving the lowest
standby power state. All operations are paused, the internal
clock is stopped, the booster circuit and OTG VBUS charge
pump are all powered down, and the USB transceivers are
powered down. All counters and timers are paused but will
retain their values. SLEEP mode exits by any activity selected
in this register. When SLEEP mode ends, instruction
execution resumes within 0.5 ms.
1: Enable Sleep Mode
0: No Function
Wake Enable
Reserved
OTG
R/W
11
0
3
0
-
Reserved
Boost 3V
OK
10
R
0
2
0
-
Wake Enable
Enable
Sleep
HSS
R/W
R/W
9
0
1
0
CY7C67200
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Wake Enable
Enable
R/W
R/W
SPI
Halt
8
0
0
0
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