CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 58

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
CRC Enable (Bit 13)
The CRC Enable bit enables or disables the CRC operation.
1: Enables CRC operation
0: Disables CRC operation
CRC Clear (Bit 12)
The CRC Clear bit will clear the CRC with a load of all ones.
This bit is self clearing and always reads ‘0’.
1: Clear CRC with all ones
0: No Function
Receive CRC (Bit 11)
The Receive CRC bit determines whether the receive bit
stream or the transmit bit stream is used for the CRC data input
in full duplex mode. This bit is a don’t care in half-duplex mode.
1: Assigns the receive bit stream
0: Assigns the transmit bit stream
SPI CRC Value Register [0xC0D4] [R/W]
Register Description
The SPI CRC Value register contains the CRC value.
CRC (Bits [15:0])
The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value will be a seven bit value [6:0]. Therefore bits [15:7]
are invalid in CRC7 mode.
SPI Data Register [0xC0D6] [R/W]
Register Description
The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO
byte mode. This receive data is valid when the receive bit of the SPI Interrupt Value is set to ‘1’ (RxIntVal triggers) or the Receive
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
R/W
R/W
15
15
X
X
1
7
1
7
-
R/W
R/W
R/W
14
14
1
6
1
X
X
6
-
Figure 67. SPI CRC Value Register
R/W
R/W
R/W
13
13
Figure 68. SPI Data Register
1
5
1
X
X
5
-
R/W
R/W
R/W
12
12
1
4
1
X
4
X
-
One in CRC (Bit 10)
The One in CRC bit is a read-only bit that indicates if the CRC
value is all zeros or not.
1: CRC value is not all zeros
0: CRC value is all zeros
Zero in CRC (Bit 9)
The Zero in CRC bit is a read-only bit that indicates if the CRC
value is all ones or not.
1: CRC value is not all ones
0: CRC value is all ones
Reserved
All reserved bits must be written as ‘0’.
Reserved
CRC...
...CRC
Data
R/W
R/W
R/W
11
11
1
3
1
X
3
X
-
R/W
R/W
R/W
10
10
X
X
1
2
1
2
-
R/W
R/W
R/W
9
1
1
1
X
X
9
1
-
CY7C67200
Page 58 of 78
R/W
R/W
R/W
8
1
0
1
X
X
8
0
-
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