CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 21

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Host n Address Register [R/W]
Register Description
The Host n Address register is used as the base pointer into
memory space for the current host transactions.
Host n Count Register [R/W]
Register Description
The Host n Count register is used to hold the number of bytes
(packet length) for the current transaction. The maximum
packet length is 1023 bytes in ISO mode. The Host Count
value is used to determine how many bytes to transmit, or the
maximum number of bytes to receive. If the number of
received bytes is greater then the Host Count value then an
overflow condition will be flagged by the Overflow bit in the
Host n Endpoint Status register.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Host 1 Address Register 0xC082
• Host 2 Address Register 0xC0A2
• Host 1 Count Register 0xC084
• Host 2 Count Register 0xC0A4
R/W
R/W
R/W
15
15
0
7
0
0
7
0
-
R/W
R/W
R/W
14
14
0
6
0
0
6
0
-
Figure 19. Host n Address Register
Figure 20. Host n Count Register
R/W
R/W
R/W
13
13
0
5
0
0
5
0
-
Reserved
R/W
R/W
R/W
12
12
4
0
4
0
0
0
-
Address (Bits [15:0])
The Address field sets the address pointer into internal RAM
or ROM.
Count (Bits [9:0])
The Count field sets the value for the current transaction data
packet length. This value is retained when switching between
host and device mode, and back again.
Reserved
All reserved bits must be written as ‘0’.
...Address
Address...
...Count
R/W
R/W
R/W
11
11
3
0
3
0
0
0
-
R/W
R/W
R/W
10
10
2
0
2
0
0
0
-
R/W
R/W
R/W
R/W
1
0
1
0
9
0
9
0
CY7C67200
Count...
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R/W
R/W
R/W
R/W
0
0
0
0
8
0
8
0
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