CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 25

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Host n Interrupt Enable Register [R/W]
Register Description
The Host n Interrupt Enable register allows control over
host-related interrupts.
In this register a bit set to ‘1’ enables the corresponding
interrupt while ‘0’ disables the interrupt.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG
VBUS interrupt. When enabled this interrupt triggers on both
the rising and falling edge of VBUS at the 4.4V status (only
supported in Port 1A). This bit is only available for Host 1 and
is a reserved bit in Host 2.
1: Enable VBUS interrupt
0: Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID
interrupt. When enabled this interrupt triggers on both the
rising and falling edge of the OTG ID pin (only supported in
Port 1A). This bit is only available for Host 1 and is a reserved
bit in Host 2.
1: Enable ID interrupt
0: Disable ID interrupt
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the
SOF/EOP timer interrupt.
1: Enable SOF/EOP timer interrupt
0: Disable SOF/EOP timer interrupt
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Host 1 Interrupt Enable Register 0xC08C
• Host 2 Interrupt Enable Register 0xC0AC
Reserved
Interrupt Enable
7
0
-
VBUS
R/W
15
0
Wake Interrupt Enable
ID Interrupt
Port A
R/W
Enable
6
0
R/W
14
0
Figure 25. Host n Interrupt Enable Register
Reserved
13
0
-
5
0
-
Interrupt Enable
Port A Connect
12
0
Change
-
R/W
Port A Wake Interrupt Enable (Bit 6)
The Port A Wake Interrupt Enable bit enables or disables the
remote wakeup interrupt for Port A.
1: Enable remote wakeup interrupt for Port A
0: Disable remote wakeup interrupt for Port A
Port A Connect Change Interrupt Enable (Bit 4)
The Port A Connect Change Interrupt Enable bit enables or
disables the Connect Change interrupt on Port A. This
interrupt triggers when either a device is inserted (SE0 state
to J state) or a device is removed (J state to SE0 state).
1: Enable Connect Change interrupt
0: Disable Connect Change interrupt
Done Interrupt Enable (Bit 0)
The Done Interrupt Enable bit enables or disables the USB
Transfer Done interrupt. The USB Transfer Done triggers
when either the host responds with an ACK, or a device
responds with any of the following: ACK, NAK, STALL, or
Timeout. This interrupt is used for both Port A and Port B.
1: Enable USB Transfer Done interrupt
0: Disable USB Transfer Done interrupt
Reserved
All reserved bits must be written as ‘0’.
Reserved
4
0
11
0
-
3
0
-
10
0
-
Reserved
2
0
-
Interrupt Enable
SOF/EOP
R/W
1
0
-
9
0
CY7C67200
Interrupt Enable
Page 25 of 78
Done
Reserved
R/W
0
0
8
0
-
[+] Feedback