CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 53

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
mode this read only bit indicates if any of the endpoint inter-
rupts occurs on Device 2. Firmware needs to determine which
endpoint interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Done1 Flag (Bit 2)
In host mode the Done 1 Flag bit is a read-only bit that
indicates if a host packet done interrupt occurs on Host 1. In
device mode this read-only bit indicates if any of the endpoint
interrupts occurs on Device 1. Firmware needs to determine
which endpoint interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
SPI Registers
There are 12 registers dedicated to SPI operation. Each register is covered in this section and summarized in
Table 33.SPI Registers
SPI Configuration Register [0xC0C8] [R/W]
Register Description
The SPI Configuration register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
SPI Configuration Register
SPI Control Register
SPI Interrupt Enable Register
SPI Status Register
SPI Interrupt Clear Register
SPI CRC Control Register
SPI CRC Value
SPI Data Register
SPI Transmit Address Register
SPI Transmit Count Register
SPI Receive Address Register
SPI Receive Count Register
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Active Enable
Enable
Master
3Wire
R/W
15
Register Name
R
1
7
0
Master
Enable
Phase
Select
R/W
R/W
14
0
6
0
Figure 61. SPI Configuration Register
SCK Polarity
Enable
Select
R/W
R/W
SS
13
0
5
0
R/W
R/W
12
0
4
1
Reset1 Flag (Bit 1)
The Reset1 Flag bit is a read-only bit that indicates if a USB
Reset interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Mailbox Out Flag (Bit 0)
The Mailbox Out Flag bit is a read-only bit that indicates if a
message is ready in the outgoing mailbox. This interrupt clears
when the external host reads from the HPI Mailbox register.
1: Interrupt triggered
0: Interrupt did not trigger
Address
0xC0CA
0xC0CC
0xC0CE
0xC0DA
0xC0DC
0xC0DE
0xC0C8
0xC0D0
0xC0D2
0xC0D4
0xC0D6
0xC0D8
R/W
R/W
11
0
3
1
Scale Select
SS Delay Select
R/W
R/W
10
0
2
1
R/W
R/W
9
0
1
1
CY7C67200
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
Table
Page 53 of 78
Reserved
33.
R/W
8
0
0
1
-
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