CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 48

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
HSS Transmit Address Register [0xC07C] [R/W]
Register Description
The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block transmit transfer.
HSS Transmit Counter Register [0xC07E] [R/W]
Register Description
The HSS Transmit Counter register designates the block byte
length for the next HSS transmit transfer. This register must be
loaded with the word count minus one to start the block
transmit transfer. As each byte is transmitted this register
value is decremented. When read, this register indicates the
remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one
giving a maximum value of 0x03FF (1023) or 2048 bytes.
When the transfer is complete this register returns 0x03FF
until reloaded.
Reserved
All reserved bits must be written as ‘0’.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
R/W
R/W
15
15
0
7
0
0
7
0
-
R/W
R/W
R/W
14
14
0
6
0
0
6
0
-
Figure 54. HSS Transmit Address Register
Figure 55. HSS Transmit Counter Register
R/W
R/W
R/W
13
13
0
5
0
0
5
0
-
Reserved
R/W
R/W
R/W
12
12
4
0
0
0
4
0
-
HPI Registers
There are five registers dedicated to HPI operation. In
addition, there is an HPI status port which can be address over
HPI. Each of these registers is covered in this section and are
summarized in
Table 32.HPI Registers
...Address
Address...
...Counter
HPI Breakpoint Register
Interrupt Routing Register
SIE1msg Register
SIE2msg Register
HPI Mailbox Register
Register Name
R/W
R/W
R/W
11
11
3
0
0
0
3
0
-
Table
32.
R/W
R/W
R/W
10
10
2
0
0
0
2
0
-
Address
0xC0C6
0x0140
0x0142
0x0144
0x0148
R/W
R/W
R/W
R/W
1
0
9
0
9
0
1
0
CY7C67200
Counter...
Page 48 of 78
R/W
R/W
R/W
R/W
R/W
R/W
0
0
8
0
8
0
0
0
W
W
R
R
[+] Feedback